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| SL2610 Wide Dynamic Range Image Reject MOPLL Data Sheet Features * * * * * * * * * Single chip mixer/oscillator PLL combination for multi band tuner for DTT applications Each mixer oscillator band optimized for wide dynamic range RF input stages allow for either single-ended or differential drive PLL frequency synthesizer designed for low phase noise performance Broadband output level detect with onset adjust PLL frequency synthesizer compatible with standard digital terrestrial offsets Four integrated switching ports I2C fast mode compliant ESD protection (Normal ESD handling procedures should be observed) SL2610/IG/LH1Q SL2610/IG/LH1N SL2610/IG/LH2Q SL2610/IG/LH2N October 2004 Ordering Information 40 40 40 40 Pin Pin Pin Pin MLP MLP MLP MLP Tape & Reel, Bake & Drypack Trays, Bake & Drypack Tape & Reel, Bake & Drypack* Trays, Bake & Drypack* *Leadfree -40C to +85C Description The SL2610 is a mixer oscillator intended primarily for application in all band tuners, where it performs image reject downconversion of the RF channel to a standard 36 MHz or 44 MHz IF. Each band consists of a low noise preamplifier/mixer and local oscillator with an external varactor tuned tank. The band outputs share a common low impedance SAWF driver stage. Frequency selection is controlled by the on-board I2C bus frequency synthesizer. This block also controls four general purpose switching ports for selecting the prefilter/AGC stages. Applications * * * * Terrestrial digital receiver systems Terrestrial analogue receiver systems Cable receiver systems Data communications systems LO HI MID BAND BAND BAND CHARGE PUMP DRIVE PROG DIVIDER ~ ~ ~ IF SELECT XTAL XTALCAP ~ REF DIVIDER CONVOP CONVOPB IFIP IFIPB IFOP IFOPB AGC BIAS AGC OUT PORT P0 PORT P1 PORT P2 PORT P3 Port Interface I2C Interface SDA SCL ADD HI LO MID BAND BAND BAND Figure 1 - SL2610 Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003-2004, Zarlink Semiconductor Inc. All Rights Reserved. SL2610 Data Sheet The SL2610 has high intermodulation intercept performance so offering high signal to spurious performance in the presence of higher amplitude interferers or in the presence of a wide bandwidth composite input signal. An output broadband level detect circuit is included for control of the tuner front end AGC. LOLOWOPB LOMIDOPB LOLOWOP LOMIDOP LOHIOPB LOHIIPB LOHIOP LOHIIP VccLO PORT P3 VccRF HI INPUT HI INPUTB PORT P2 PORT P1 MID INPUT MID INPUTB VccRF LO INPUT Pin 1 VccLO IFOPB IFOP AGCBIAS VCCIF IFIPB IFIP ADD CONVOP CONVOPB VccDIG LO INPUTB PORT P0 AGCOUT CHARGE PUMP XTAL CAP VccRF DRIVE XTAL SDA SCL VEE (PACKAGE PADDLE) LH40 Figure 2 - Pin Allocation Diagram Quick Reference Data Characteristics Frequency range: LOW band MID band HIGH band Conversion gain * Noise figure Typical Image Reject P1dB input referred, Converter section only IP3 input referred, Converter section only IP2 input referred, Converter section only LO phase noise (free running) @ 10 kHz offset @ 100 kHz offset PLL phase noise Maximum composite output amplitude * Assuming 2 dB shaping filter loss in external IF path. 50-500 50-500 200-900 32 2 13 35 106 14 48 -90 -110 -158 3 Units MHz MHz MHz dB dB dB dBuV dBm dBm dBc/Hz dBc/Hz dBc/Hz dBm 2 Zarlink Semiconductor Inc. R5 1K 8n2H L6 VT 1K BB555 5pF 36nH R2 1K R3 L3 C28 1 100nF +30V 100pF C16 D3 C15 +30V C9 D2 4K7 R6 L5 R19 3 gnd +5V gnd +5V 2 GND 10R 22nH POWER 100pF L1 120nH BB640 4K7 82nH +5V 7pF 2p2 470uF 2p2 2p2 2p2 D1 100pF C1 R4 L4 C10 C36 BB640 gnd CN2 C11 C12 C13 C14 C2 1u5H 37 40 38 39 35 34 36 33 32 31 6p8F 20R gnd gnd VccLO VccLO gnd +5V PORT P3 Vcc RF IF O/P 29 IF O/P B 4K7 P3 1 30 2 L2 gnd 10nF 10R 10R 10nF C30 gnd R17 R18 C32 R16 LOHII/P LOHIO/P LOHII/PB R1 10nF C22 T1 IF OUT SK4 IF OUT +5V gnd LOMIDOP LOLOWOP C29 10nF LOLOWOPB LOMIDOPB LOHIO/PB C3 SK1 HI IN HIGH IP HIGH IP B Vcc IF IF INPUT B Vee = Pin 0 = PACKAGE PADDLE IF INPUT ADD CONV OP CONV OP B Vcc DIG XTAL SDA SCL Gnd 26 25 24 27 AGC BIAS gnd 3 28 C23 10nF 5:1 gnd +5V TP2 TP RF IN (HIGH) C4 1nF 4 gnd gnd 1nF VR1 10K AGC C24 1nF IC1 SL2610 P2 PORT P2 PORT P1 MID INPUT MID IP B Vcc RF LO INPUT 5 6 7 C26 82pF C33 gnd 10nF SL2610 LO INPUT B Vcc RF AGC OUT PORT P0 DRIVE CHARGE PUMP XTAL CAP C8 gnd 11 12 13 14 15 16 gnd 1nF +5V +5V 0 17 18 19 20 gnd gnd gnd +5V P0 C34 D4 P0 P0 gnd +30V 10nF 10K R12 R20 C19 C18 C17 100nF 47pF 47pF R10 4K7 R11 4K7 Figure 3 - SL2610 Evaluation Board Schematic C25 1nF 220nH +5V 750R CN1 X1 R13 P1 P1 VT D5 R8 20K TP1 TP gnd 3 Zarlink Semiconductor Inc. P1 C35 gnd 9 1nF 22 2 10nF 1 3 C5 SK2 MID IN L7 gnd RF IN (MID) C6 1nF +5V 8 gnd L8 23 C27 82pF 220nH C7 SK3 gnd 10 1nF LOW IN CN3 +5V 21 ADDRESS ADDRESS RF IN (LOW) C31 10nF 3 4 5 6 750R R7 33K 4 MHz SDA VDD GND SCL I2C Control C20 47pF gnd I2C R14 P2 18K P2 D6 R9 C21 1n5F 750R R15 P3 P3 D7 gnd TR1 BCW31 gnd Data Sheet 750R SL2610 Data Sheet Figure 4 - SL2610 Evaluation Board Layout (Top) Figure 5 - SL2610 Evaluation Board Layout (Bottom) 4 Zarlink Semiconductor Inc. SL2610 1.0 Functional Description Data Sheet The SL2610 is a multi band RF mixer oscillator with image reject and on-board frequency synthesizer. It is intended primarily for application in all band terrestrial tuners and requires a minimum external component count. It contains all elements required for RF downconversion to a standard IF with the exception of external VCO tank circuits. The pin allocation is contained in Figure 2 and the block diagram in Figure 1. 1.1 Mixer/oscillator section In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner prefilter and AGC stages. The mixer input is arranged such that the signal can be coupled either differentially or single-ended, and achieves the specified minimum performance in both configurations. Band input impedances and NF are contained in Figure 11 and Figure 12 respectively. The converter two tone input spectra are contained in Figure 13 and Figure 14. The preamplifier output then feeds the mixer stage where the required channel is image reject downconverted to the IF frequency. The local oscillator frequency for the downconversion is obtained from the on board local oscillator, which uses an external varactor tuned tank. Typical VCO applications are contained in Figures 8, 9 and 10. The output of the mixer is then fed to the converter output driver which presents a matched 200 differential load to an external IF shaping filter. The output of the shaping filter is then coupled into the IFAMP stage, which provides further gain and offers a 50 output impedance to interface direct with the tuner SAW filter. The SL2610 contains a broadband level detect circuit whose output can be used to control the tuner AGC. The target level of the AGC detector is controlled by the voltage applied to the AGCBIAS pin. The characteristic of the target level is given in Figure 18. 1.2 PLL Frequency Synthesizer The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency reference and loop filter, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. It can also be operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers. The LO signal is multiplexed from the selected oscillator section to an internal preamplifier which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider which is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits and the M counter is 11 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1. The output of the phase detector feeds a charge pump and loop amplifier section which when used with an external loop filter integrates the current pulses into the varactor line voltage. The programmable divider output Fpd, divided by two and the reference divider output Fcomp, can be switched to port P0 by programming the device into test mode. The test modes are described in Table 5. 5 Zarlink Semiconductor Inc. SL2610 2.0 Programming Data Sheet The SL2610 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesizer can either accept data (write mode) or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low and read mode if it is high. Tables 2 and 3 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesizer in an I2C bus system (Tables 2 and 3). Table 4 shows how the address is selected by applying a voltage to the `ADD' input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period the device generates an internal STOP condition which inhibits further reading. 2.1 Write mode With reference to Table 2, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the reference divider ratio bits R4-R0 (Table 1) and the charge pump setting bits C1-C0 (Table 6). Byte 5 controls the IF select (Table 8), the band select function bits BS1-BS0 (Table 7), the switching ports P3-P0 and the test modes (Table 5). After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2 and a logic '1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. 2.2 Read mode When the device is in read mode, the status byte read from the device takes the form shown Table 3. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3V (at 25oC), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to power up condition. Bit 2 (FL) indicates whether the device is phase locked, a logic '1' is present if the device is locked and a logic '0' if the device is unlocked. 6 Zarlink Semiconductor Inc. SL2610 2.3 Programmable features Function as described above. Function as described above. Data Sheet Synthesiser programmable divider Reference programmable divider Band selection IF selection Charge pump current Ports P3-P0 The required mixer oscillator band and RF input is selected by bits BS1-BS0, within data byte 5, as defined in Table 7. The centre of the image reject passband is selected by IF as defined in Table 8. The charge pump current can be programmed by bits C1-C0 within data byte 4, as defined in Table 6. These are configured as NPN open collector buffers and programmed by bits P3P0. Logic `1' = on. Logic `0' = off (high impedance); default on power up. In test modes, when TE=1, ports P3-P0 respond according to T2-T0 respectively and previously transmitted data is lost. The test modes are invoked by setting bits T2-T0 as described in Table 5. Test mode 7 Zarlink Semiconductor Inc. SL2610 R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ratio 2 4 8 16 32 64 128 256 not allowed 5 10 20 40 80 160 320 not allowed 6 12 24 48 96 192 384 not allowed 7 14 28 56 112 224 448 Data Sheet Table 1 - Reference Division Ratio 8 Zarlink Semiconductor Inc. SL2610 MSB Address Programmable divider Programmable divider Control data Control data 1 0 27 1 IF 1 214 26 C1 BS1 0 213 25 C0 BS0 0 212 24 R4 TE 0 211 23 R3 P3/T2 MA1 210 22 R2 P2/T1 MA0 29 21 R1 P1/T0 LSB 0 28 20 R0 P0 Data Sheet A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Table 2 - Write Data Format (MSB is transmitted first) MSB Address Status Byte 1 POR 1 FL 0 0 0 0 0 0 MA1 0 MA0 0 LSB 1 0 A A Byte 1 Byte 2 Table 3 - Read Data Format (MSB is transmitted first) A MA1,MA0 2 -2 14 0 : : : : : : : : : : : : Acknowledge bit Variable address bits (see Table 4) Programmable division ratio control bits Reference division ratio select (see Table 1) Charge pump current select (see Table 6) Band select bits (see Table 7) IF passband select (see Table 8) Test mode enable Test mode control bits when TE=1 (see Table 5) P3-P0 port output states Power on reset indicator Phase lock flag R4-R0 C1,C0 BS1-BS0 IF TE T2-T0 P3-P0 POR FL 9 Zarlink Semiconductor Inc. SL2610 MA1 0 0 1 1 MA0 0 1 0 1 Address Input Voltage Level 0-0.1Vcc Open circuit 0.4Vvcc - 0.6 Vcc # 0.9 Vcc - Vcc Data Sheet # Programmed by connecting a 30 k resistor between pin and Vcc Table 4 - Address Selection TE 0 1 1 1 1 1 1 T2 X 0 0 0 0 1 1 T1 X 0 0 1 1 0 0 T0 X 0 1 0 1 0 1 Normal operation Normal operation Test Mode Description Charge pump sink * Status byte FL set to logic `0' Charge pump source * Status byte FL set to logic `0' Charge pump disabled * Status byte FL set to logic `1' Normal operation and Port P0 = Fpd/2 Charge pump sink * Status byte FL set to logic `0' Port P0 = Fcomp Charge pump source * Status byte FL set to logic `0' Port P0 = Fcomp Charge pump disabled * Status byte FL set to logic `1' Port P0 = Fcomp Table 5 - Test Modes 1 1 1 0 1 1 1 1 * crystal and selected local oscillator need signals to enable charge pump test modes and to toggle status byte bit FL X -'don't care' 10 Zarlink Semiconductor Inc. SL2610 C1 C0 Min. 0 0 1 1 0 1 0 1 +85 +190 +420 +930 Current in A Typ. +130 +280 +600 +1300 Max. +175 +370 +780 +1670 Data Sheet Table 6 - Charge pump current BS1 0 0 1 1 BS0 0 1 0 1 Band Selected LO Band MID Band HI band HI band Table 7 - Band select IF input 0 0 1 Centre of Image Reject Passband 57 MHz 44 MHz 36 MHz Table 8 - IF SELECT function Passband Bandwidth 6 MHz 6 MHz 8 MHz 11 Zarlink Semiconductor Inc. SL2610 Data Sheet XTALCAP 47 pF SL2610 47 pF XTAL Figure 6 - Crystal Oscillator Application IFOPB SL2610 IFOP 5:1 to 50 load Figure 7 - Ifamp Output Load Condition for Test Purposes C2 L1 120nH D1 BB640 7pF R16 20R R1 4K7 L2 1u5H R2 1K VT C1 100pF LOLOWOP LOLOWOPB Figure 8 - LO Band VCO Application 12 Zarlink Semiconductor Inc. SL2610 VT Data Sheet R3 1K L3 R4 4K7 C9 100pF D2 BB640 C10 7pF 36nH L4 82nH LOMIDOP LOMIDOPB Figure 9 - Mid Band VCO Application VT R5 1K L6 8.2nH C16 100pF C15 D3 BB555 5pF R6 4K7 L5 22nH R19 10R C11 2p2 C12 2p2 C13 2p2 C14 2p2 R17 10R R18 10R LOHIIP LOHIOP LOHIOPB LOHIIPB Figure 10 - HI Band VCO Application 13 Zarlink Semiconductor Inc. SL2610 Data Sheet CH1 S 11 1 U FS DEV1 VCC=4.7V 1_: 152.31 12 Mar 2002 15:10:11 -12.117 145.94 pF 90.000 000 MHz PRm Cor 2_: 150.74 -34.063 220 MHz 3_: 133.48 -62.813 500 MHz 4_: 111.79 -86.926 900 MHz 1 2 3 4 START 50.000 000 MHz STOP 900.000 000 MHz Figure 11 - LO, MID and HI Band Input Impedance Figure 12 - Low, Mid and Hi Band Noise Figure versus Frequency 14 Zarlink Semiconductor Inc. SL2610 Data Sheet -14 dBm Incident power from 50 source IIM3; -42 dBc -56 dBm df (6 MHz) f1-df f1 f2 f2+df Figure 13 - Converter Third Order Two Tone Intermodulation Test Condition Spectrum, Input Referred, All Bands Incident power from 50 source -14 dBm IIM2; -40 dBc -54 dBm df f2-f1 f1 f2 X Figure 14 - Second Order Two Tone Intermodulation Test Condition Spectrum, Input Referred 15 Zarlink Semiconductor Inc. SL2610 Data Sheet CH1 S 11 1 U FS DEV4 5.3V 3_: 101.43 26 Nov 2002 13:38:57 -8.0313 347.67 pF 57.000 000 MHz PRm 1_: 102.92 -5.043 36 MHz 2_: 102.48 -6.4883 44 MHz 3 1 2 START 32.000 000 MHz STOP 60.000 000 MHz Figure 15 - Converter Output Impedance (Single Ended) CH1 S 11 1 U FS 1_: 173.88 27 Nov 2002 09:17:33 11.094 49.045 nH 36.000 000 MHz PRm C? Avg 16 2_: 178.89 10.016 44 MHz 3_: 185.77 04.922 57 MHz 1 2 3 START 30.000 000 MHz STOP 60.000 000 MHz Figure 16 - IFAMP Input Impedance 16 Zarlink Semiconductor Inc. SL2610 Data Sheet CH1 S 11 1 U FS 1_: 58.967 27 Nov 2002 08:59:45 8.8438 39.098 nH 36.000 000 MHz PRm 2_: 59.295 11.096 44 MHz 3_: 60.443 14.813 57 MHz 1 3 2 START 30.000 000 MHz STOP 60.000 000 MHz Figure 17 - IFAMP Output Impedance (Single Ended) 120 115 Output Level (dBV) 110 105 100 0 1 2 3 AGCBIAS Voltage (V) 4 5 6 Figure 18 - Typical AGC Output Level Set versus AGCBIAS Voltage 17 Zarlink Semiconductor Inc. SL2610 Electrical Characteristics Test conditions (unless otherwise stated) Tamb = -40oC to 85oC, Vee= 0 V, Vcc=Vcca=Vccd = 5 V +5% Data Sheet These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Supply current LO or MID BAND ENABLED Input frequency range Input impedance Input Noise Figure Converter gain 10 8.5 13 14 12.5 dB dB dB 50 500 MHz See Figure 11 and refer to Note 8. Tamb=27oC, see Figure 12, refer to Note 2, no correction for external filtering. At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Conversion gain from 50 single ended source to differential 200 load, refer to Note 3. At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Conversion gain from 50 single ended source to 50 single-ended load with output transformer as in Figure 7, see Notes 2 and 3. Channel bandwidth 8 MHz within operating frequency range, see note (2), excluding interstage shaping filter ripple. See Figure 14 and refer to Notes 4 and 6. Assuming ideal power match. See Figure 14 and refer to Notes 4 and 6. See Figure 13 and refer to Notes 4 and 6. Assuming ideal power match. See Figure 13 and refer to Notes 4 and 6. Pin Min. Typ. 163 Max. 196 Units mA Conditions All switching ports off. Conversion gain to IFAMP output 28 25 36 33 dB dB Gain variation within channel Converter input referred IP2 Converter input referred IM2 Converter input referred IP3 Converter input referred IM3 Input referred P1dB Local oscillator operation range Local oscillator tuning range 101 50 68 200 7 26 0.4 1 dB dBm -40 dBc dBm -42 dBc dBV 550 225 465 MHz MHz MHz Refer to Note 7. With application as in Figure 8. With application as in Figure 9. 18 Zarlink Semiconductor Inc. SL2610 Characteristic LO phase noise, SSB @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset LO temperature stability 80 LO turn on drift kHz/oC Pin Min. Typ. Max. -55 -86 -109 Units dBc/Hz dBc/Hz dBc/Hz Conditions Data Sheet With application as in Figure 8 and Figure 9 outside of PLL loop bandwidth. Application as in Figure 8 and Figure 9. No temperature compensation. Application as in Figure 8 and Figure 9, frequency drift over 15 minute period from turn on at a fixed ambient temperature. No temperature compensation. Application as in Figures 8 and 9. 100 LO to RF input leakage LO Vcc stability LO spurs due to RF pulling HI BAND ENABLED Input frequency range Input impedance Input Noise Figure 13.5 200 870 60 0.5 -52 kHz dBV MHz/V dBc See Note 5. MHz See Figure 11 and refer to Note 8. dB Tamb=27oC, see Figure 12, refer to Note 2, no correction for external filtering. At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Conversion gain from 50 single ended source to differential 200 load, refer to Note 3. At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Conversion gain from 50 single ended source to 50 single-ended load with output transformer as in Figure 7, see Notes 2 and 3. Channel bandwidth 8 MHz within operating frequency range, see Note 3, excluding interstage shaping filter ripple. See Figure 14 and refer to Notes 4 and 6. Assuming ideal power match. Converter gain 10 8.5 14 12.5 dB dB Conversion gain to IFAMP output 28 25 36 33 dB dB Gain variation within channel 0.4 1 dB Converter input referred IP2 26 dBm 19 Zarlink Semiconductor Inc. SL2610 Characteristic Converter input referred IM2 Converter input referred IP3 Converter input referred IM3 Input referred P1dB Local oscillator operation range Local oscillator tuning range LO phase noise, SSB @ 1 kHz offset @ 10 kHz offset @ 100 kHz offset LO temperature stability 110 LO turn on drift 100 LO to RF input leakage LO Vcc stability LO spurs due to RF pulling All Bands Converter output impedance Image rejection 25 29 25 200 30 35 30 dB dB dB 60 0.5 -52 kHz dBV MHz/V dBc See Note 5. 101 200 440 1000 950 7 -42 Pin Min. Typ. Max. -40 Units dBc dBm dBc dBV MHz MHz Refer to Note 7. With application as in Figure 10. Conditions Data Sheet See Figure 14 and refer to Notes 4 and 6. See Figure 13 and refer to Notes 4 and 6. Assuming ideal power match. See Figure 13 and refer to Notes 4 and 6. -55 -86 -109 dBc/Hz dBc/Hz dBc/Hz kHz/oC With application as in Figure 10, outside of PLL loop bandwidth. Application as in Figure 10. No temperature compensation. Application as in Figure 10, frequency drift over 15 minute period from turn on at a fixed ambient temperature. No temperature compensation. Application as in Figure 10. Differential, see Figure 15. At 36 MHz IF frequency, IF bit = 1. At 44 MHz IF frequency, IF bit = 0. At 57 MHz IF frequency, IF bit = 0. See Table 8. Tamb = 0oC to +85oC. Tank Schematics and layouts as in recommended application. See Figures 4 and 5. Level of desired signal converted to IF output through disabled band relative to signal converted through enabled band. Isolation between band inputs -60 dBc Composite output amplitude 3 dBm 20 Zarlink Semiconductor Inc. SL2610 Characteristic IFAMP Input frequency range Input impedance Gain 20 18.5 32 200 24 22.5 60 MHz dB dB Pin Min. Typ. Max. Units Conditions Data Sheet Differential, see Figure 16. At 36 MHz and 44 MHz IF frequency. At 57 MHz IF frequency. Voltage conversion gain from 200 differential source to differential load as contained in Figure 7, see Note 3. Differential, see Figure 17. At 36 MHz and 44 MHz IF fequency. At 57 MHz IF frequency. Differential into load as in Figure 7. Two output tones at 2 MHz separation at 104 dBuV into load as in Figure 7, see Note 2. Two output tones at 2 MHz separation at 104 dBuV into load as in Figure 7, see Note 2. Vee Vagc1 Vcc 1.5V Vagc1 3.5V Max load current 20 A. See Figure 18. Output impedance Output limiting 3 2.7 135 100 Vp-p Vp-p dBV IFAMP OPIP3 IFAMP OPIM3 -62 dBc AGCBIAS Leakage current AGCOUT voltage range AGC output level set Supply rejection 28 13 -100 -50 0.5 100 50 3 A A V -52 dBc Spurs introduced on converted output relative to desired signal by a supply ripple voltage of 10 mV p-p in the range 1 kHz to 100 kHz (including external supply decoupling). Synthesiser SDA, SCL Input high voltage Input low voltage Input current Leakage current Hysterysis 19, 20 3 0 -10 19, 20 0.4 5.5 1.5 10 10 V V A A V Input voltage =Vee to Vcc Input voltage = Vee to 5.5 V, Vcc=Vee SDA output voltage SCL clock rate 19 20 0.4 0.6 400 V V kHz Isink = 3 mA Isink = 6 mA 21 Zarlink Semiconductor Inc. SL2610 Characteristic Charge pump output current Charge pump output leakage Charge pump drive output current Crystal frequency Recommended crystal series resonance External reference input frequency External reference drive level Phase detector comparison frequency Equivalent phase noise at phase detector -158 RF division ratio Reference division ratio Switching ports P0-P3 sink current leakage current Address select Input high current Input low current 1, 5, 6, 14 24 1 -0.5 mA mA 10 10 mA A 240 32767 See Table 1. Vport = 0.7 V Vport = Vcc See Table 4. Vin=Vcc Vin=Vee 17, 18 18 Pin 16 16 15 17, 18 0.5 4 10 4 0.2 .03125 16 200 20 0.5 0.25 +3 +10 nA mA MHz MHz Vpp MHz Min. Typ. Max. Units Conditions See Table 6. Vpin16 = 2 V Vpin16 = 2 V Vpin15 = 0.7 V Data Sheet Application as in Figure 6. 4 MHz parallel resonant crystal. Sinewave coupled through 10 nF blocking capacitor. Sinewave coupled through 10 nF blocking capacitor. With 4 MHz crystal, SSB, within loop bandwidth. With Fcomp = 125 kHz Notes 1 All power levels are referred to 50 , and 0 dBm = 107 dBV. 2 Total system with final load as in Figure 7, including an interstage IF shaping filter with IL of 2 dB and characteristic impedance of 200 differential. 3 The specified gain is determined by the following formula; Gs = Gm + Vtr where Gs = gain as specified Gm = gain as measured with specified load conditions Vtr = voltage transformation ratio of transformer as in Figure 7 4 Two input tones within RF operating range at -14 dBm from 50 single ended source with 200 differential output load. DC output current must be shunted to Vcc through suitable inductor, i.e. 10 H. 5 Modulation spurs introduced on local oscillator through injection locking of the local oscillator by an undesired RF carrier. Desired carrier at 80 dBV, undesired carrier at 90 dBV at an offset frequency of fd plus 42+fc MHz, where fd is desired carrier frequency, fc is US chrominance sub carrier and 42 equals 7 channel spacings. 6 All intermodulation specifications are measured with a single-ended input. 7 Operation range is defined as the region over which the oscillator presents a negative impedance. 8 Target to achieve 6 dB minimum S11. 22 Zarlink Semiconductor Inc. SL2610 Absolute Maximum Ratings All voltages are referred to Vee at 0 V. Characteristic Supply voltage RF input voltage All I/O port DC offsets Total port current Storage temperature Junction temperature Package thermal resistance, chip to ambient Power consumption at 5.25V ESD protection 1 -55 -0.3 Min. -0.3 Max. 6 117 Vcc+0.3 20 150 125 27 1 o Data Sheet Units V dBV V mA o o Conditions Transient condition only. C C Power applied. Package paddle soldered to ground. C/W W kV Mil-std 883B method 3015 cat1 23 Zarlink Semiconductor Inc. SL2610 VCC Data Sheet VCC 3, 7, 10 IP Typical 133-j62 @ 500 MHz (see Figure 10) 4, 8, 11 IPB 1 nF External to Chip 50 29 IFOPB IFOP 30 50 LOW, MID, HI, RF Input IF Output VCC 400 34 LOHIOP 400 13 20K 33 AGCOUT LOHIIP Vbias 35 500 LOHIOPB 32 LOHIPB AGC Out LOHI Input & Output 100 100 23 22 CONVOPB CONVOP LOLOWOP 38 LOMIDOP 40 37 LOLOWOPB 39 LOMIDOPB Vbias Converter Output VCC LOLOW and LOMID Outputs VCC IFIP 25 IFIPB 26 95 1.38 K 28 40 K AGCBIAS 9K 2.4 V IF Input AGCBIAS Input Figure 19 - Input and Output Interface Circuits (RF Section) 24 Zarlink Semiconductor Inc. SL2610 Data Sheet Vccd Vccd 16 XTAL 18 13 220 200 A PUMP XTALCAP 17 15 DRIVE Reference oscillator Loop amplifier Vccd Vccd 120 K 500 K SCL/SDA 24 ADD 40 K * ACK * On SDA only SDA/SCL (pins 19 and 20) ADD input P0, P1, P2, P3 Output Ports (pins 1, 5, 6, 14) Figure 20 - Input and Output Interface Circuits (PLL Section) 25 Zarlink Semiconductor Inc. For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. 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